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Independent SDK for the Sega Dreamcast
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Networking » Drivers » Broadband Adapter » Registers

Locations for various broadband adapter registers. More...

Macros

#define RT_IDR0   0x00
 MAC address 0 (RW 32bit, RO 16/8)
 
#define RT_IDR1   0x01
 MAC address 1 (Read-only)
 
#define RT_IDR2   0x02
 MAC address 2 (Read-only)
 
#define RT_IDR3   0x03
 MAC address 3 (Read-only)
 
#define RT_IDR4   0x04
 MAC address 4 (RW 32bit, RO 16/8)
 
#define RT_IDR5   0x05
 MAC address 5 (Read-only)
 
#define RT_RES06   0x06
 Reserved.
 
#define RT_RES07   0x07
 Reserved.
 
#define RT_MAR0   0x08
 Multicast filter 0 (RW 32bit, RO 16/8)
 
#define RT_MAR1   0x09
 Multicast filter 1 (Read-only)
 
#define RT_MAR2   0x0A
 Multicast filter 2 (Read-only)
 
#define RT_MAR3   0x0B
 Multicast filter 3 (Read-only)
 
#define RT_MAR4   0x0C
 Multicast filter 4 (RW 32bit, RO 16/8)
 
#define RT_MAR5   0x0D
 Multicast filter 5 (Read-only)
 
#define RT_MAR6   0x0E
 Multicast filter 6 (Read-only)
 
#define RT_MAR7   0x0F
 Multicast filter 7 (Read-only)
 
#define RT_TXSTATUS0   0x10
 Transmit status 0 (32bit only)
 
#define RT_TXSTATUS1   0x14
 Transmit status 1 (32bit only)
 
#define RT_TXSTATUS2   0x18
 Transmit status 2 (32bit only)
 
#define RT_TXSTATUS3   0x1C
 Transmit status 3 (32bit only)
 
#define RT_TXADDR0   0x20
 Tx descriptor 0 (32bit only)
 
#define RT_TXADDR1   0x24
 Tx descriptor 1 (32bit only)
 
#define RT_TXADDR2   0x28
 Tx descriptor 2 (32bit only)
 
#define RT_TXADDR3   0x2C
 Tx descriptor 3 (32bit only)
 
#define RT_RXBUF   0x30
 Receive buffer start address (32bit only)
 
#define RT_RXEARLYCNT   0x34
 Early Rx byte count (RO 16bit)
 
#define RT_RXEARLYSTATUS   0x36
 Early Rx status (RO)
 
#define RT_CHIPCMD   0x37
 Command register.
 
#define RT_RXBUFTAIL   0x38
 Current address of packet read (queue tail) (16bit only)
 
#define RT_RXBUFHEAD   0x3A
 Current buffer address (queue head) (RO 16bit)
 
#define RT_INTRMASK   0x3C
 Interrupt mask (16bit only)
 
#define RT_INTRSTATUS   0x3E
 Interrupt status (16bit only)
 
#define RT_TXCONFIG   0x40
 Tx config (32bit only)
 
#define RT_RXCONFIG   0x44
 Rx config (32bit only)
 
#define RT_TIMER   0x48
 A general purpose counter, any write clears (32bit only)
 
#define RT_RXMISSED   0x4C
 24 bits valid, write clears (32bit only)
 
#define RT_CFG9346   0x50
 93C46 command register
 
#define RT_CONFIG0   0x51
 Configuration reg 0.
 
#define RT_CONFIG1   0x52
 Configuration reg 1.
 
#define RT_RES53   0x53
 Reserved.
 
#define RT_TIMERINT   0x54
 Timer interrupt register (32bit only)
 
#define RT_MEDIASTATUS   0x58
 Media status register.
 
#define RT_CONFIG3   0x59
 Config register 3.
 
#define RT_CONFIG4   0x5A
 Config register 4.
 
#define RT_RES5B   0x5B
 Reserved.
 
#define RT_MULTIINTR   0x5C
 Multiple interrupt select (32bit only)
 
#define RT_RERID   0x5E
 PCI Revision ID (10h) (Read-only)
 
#define RT_RES5F   0x5F
 Reserved.
 
#define RT_MII_TSAD   0x60
 Transmit status of all descriptors (RO 16bit)
 
#define RT_MII_BMCR   0x62
 Basic Mode Control Register (16bit only)
 
#define RT_MII_BMSR   0x64
 Basic Mode Status Register (RO 16bit)
 
#define RT_AS_ADVERT   0x66
 Auto-negotiation advertisement reg (16bit only)
 
#define RT_AS_LPAR   0x68
 Auto-negotiation link partner reg (RO 16bit)
 
#define RT_AS_EXPANSION   0x6A
 Auto-negotiation expansion reg (RO 16bit)
 
#define RT_CONFIG5   0xD8
 Config register 5.
 

Detailed Description

Locations for various broadband adapter registers.

The default assumption is that these are all RW at any aligned size unless otherwise noted. ex (RW 32bit, RO 16/8) indicates read/write at 32bit and read-only at 16 or 8bits.

Macro Definition Documentation

◆ RT_AS_ADVERT

#define RT_AS_ADVERT   0x66

Auto-negotiation advertisement reg (16bit only)

◆ RT_AS_EXPANSION

#define RT_AS_EXPANSION   0x6A

Auto-negotiation expansion reg (RO 16bit)

◆ RT_AS_LPAR

#define RT_AS_LPAR   0x68

Auto-negotiation link partner reg (RO 16bit)

◆ RT_CFG9346

#define RT_CFG9346   0x50

93C46 command register

◆ RT_CHIPCMD

#define RT_CHIPCMD   0x37

Command register.

◆ RT_CONFIG0

#define RT_CONFIG0   0x51

Configuration reg 0.

◆ RT_CONFIG1

#define RT_CONFIG1   0x52

Configuration reg 1.

◆ RT_CONFIG3

#define RT_CONFIG3   0x59

Config register 3.

◆ RT_CONFIG4

#define RT_CONFIG4   0x5A

Config register 4.

◆ RT_CONFIG5

#define RT_CONFIG5   0xD8

Config register 5.

◆ RT_IDR0

#define RT_IDR0   0x00

MAC address 0 (RW 32bit, RO 16/8)

◆ RT_IDR1

#define RT_IDR1   0x01

MAC address 1 (Read-only)

◆ RT_IDR2

#define RT_IDR2   0x02

MAC address 2 (Read-only)

◆ RT_IDR3

#define RT_IDR3   0x03

MAC address 3 (Read-only)

◆ RT_IDR4

#define RT_IDR4   0x04

MAC address 4 (RW 32bit, RO 16/8)

◆ RT_IDR5

#define RT_IDR5   0x05

MAC address 5 (Read-only)

◆ RT_INTRMASK

#define RT_INTRMASK   0x3C

Interrupt mask (16bit only)

◆ RT_INTRSTATUS

#define RT_INTRSTATUS   0x3E

Interrupt status (16bit only)

◆ RT_MAR0

#define RT_MAR0   0x08

Multicast filter 0 (RW 32bit, RO 16/8)

◆ RT_MAR1

#define RT_MAR1   0x09

Multicast filter 1 (Read-only)

◆ RT_MAR2

#define RT_MAR2   0x0A

Multicast filter 2 (Read-only)

◆ RT_MAR3

#define RT_MAR3   0x0B

Multicast filter 3 (Read-only)

◆ RT_MAR4

#define RT_MAR4   0x0C

Multicast filter 4 (RW 32bit, RO 16/8)

◆ RT_MAR5

#define RT_MAR5   0x0D

Multicast filter 5 (Read-only)

◆ RT_MAR6

#define RT_MAR6   0x0E

Multicast filter 6 (Read-only)

◆ RT_MAR7

#define RT_MAR7   0x0F

Multicast filter 7 (Read-only)

◆ RT_MEDIASTATUS

#define RT_MEDIASTATUS   0x58

Media status register.

◆ RT_MII_BMCR

#define RT_MII_BMCR   0x62

Basic Mode Control Register (16bit only)

◆ RT_MII_BMSR

#define RT_MII_BMSR   0x64

Basic Mode Status Register (RO 16bit)

◆ RT_MII_TSAD

#define RT_MII_TSAD   0x60

Transmit status of all descriptors (RO 16bit)

◆ RT_MULTIINTR

#define RT_MULTIINTR   0x5C

Multiple interrupt select (32bit only)

◆ RT_RERID

#define RT_RERID   0x5E

PCI Revision ID (10h) (Read-only)

◆ RT_RES06

#define RT_RES06   0x06

Reserved.

◆ RT_RES07

#define RT_RES07   0x07

Reserved.

◆ RT_RES53

#define RT_RES53   0x53

Reserved.

◆ RT_RES5B

#define RT_RES5B   0x5B

Reserved.

◆ RT_RES5F

#define RT_RES5F   0x5F

Reserved.

◆ RT_RXBUF

#define RT_RXBUF   0x30

Receive buffer start address (32bit only)

◆ RT_RXBUFHEAD

#define RT_RXBUFHEAD   0x3A

Current buffer address (queue head) (RO 16bit)

◆ RT_RXBUFTAIL

#define RT_RXBUFTAIL   0x38

Current address of packet read (queue tail) (16bit only)

◆ RT_RXCONFIG

#define RT_RXCONFIG   0x44

Rx config (32bit only)

◆ RT_RXEARLYCNT

#define RT_RXEARLYCNT   0x34

Early Rx byte count (RO 16bit)

◆ RT_RXEARLYSTATUS

#define RT_RXEARLYSTATUS   0x36

Early Rx status (RO)

◆ RT_RXMISSED

#define RT_RXMISSED   0x4C

24 bits valid, write clears (32bit only)

◆ RT_TIMER

#define RT_TIMER   0x48

A general purpose counter, any write clears (32bit only)

◆ RT_TIMERINT

#define RT_TIMERINT   0x54

Timer interrupt register (32bit only)

◆ RT_TXADDR0

#define RT_TXADDR0   0x20

Tx descriptor 0 (32bit only)

◆ RT_TXADDR1

#define RT_TXADDR1   0x24

Tx descriptor 1 (32bit only)

◆ RT_TXADDR2

#define RT_TXADDR2   0x28

Tx descriptor 2 (32bit only)

◆ RT_TXADDR3

#define RT_TXADDR3   0x2C

Tx descriptor 3 (32bit only)

◆ RT_TXCONFIG

#define RT_TXCONFIG   0x40

Tx config (32bit only)

◆ RT_TXSTATUS0

#define RT_TXSTATUS0   0x10

Transmit status 0 (32bit only)

◆ RT_TXSTATUS1

#define RT_TXSTATUS1   0x14

Transmit status 1 (32bit only)

◆ RT_TXSTATUS2

#define RT_TXSTATUS2   0x18

Transmit status 2 (32bit only)

◆ RT_TXSTATUS3

#define RT_TXSTATUS3   0x1C

Transmit status 3 (32bit only)