SH4 CPU Performance Counter Driver More...

Topics
	Timer
	High-resolution performance counter-based timer API

Files
file	perfctr.h
	Low-level performance counter API.

Enumerations
enum	perf_cntr_t { PRFC0 , PRFC1 }
	Identifiers for the two SH4 performance counters. More...

enum	perf_cntr_clock_t { PMCR_COUNT_CPU_CYCLES , PMCR_COUNT_RATIO_CYCLES }
	Count clock types for the SH4 performance counters. More...

enum	perf_cntr_event_t { PMCR_INIT_NO_MODE = 0x00 , PMCR_OPERAND_READ_ACCESS_MODE = 0x01 , PMCR_OPERAND_WRITE_ACCESS_MODE = 0x02 , PMCR_UTLB_MISS_MODE = 0x03 , PMCR_OPERAND_CACHE_READ_MISS_MODE = 0x04 , PMCR_OPERAND_CACHE_WRITE_MISS_MODE = 0x05 , PMCR_INSTRUCTION_FETCH_MODE = 0x06 , PMCR_INSTRUCTION_TLB_MISS_MODE = 0x07 , PMCR_INSTRUCTION_CACHE_MISS_MODE = 0x08 , PMCR_ALL_OPERAND_ACCESS_MODE = 0x09 , PMCR_ALL_INSTRUCTION_FETCH_MODE = 0x0a , PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE = 0x0b , PMCR_ON_CHIP_IO_ACCESS_MODE = 0x0d , PMCR_OPERAND_ACCESS_MODE = 0x0e , PMCR_OPERAND_CACHE_MISS_MODE = 0x0f , PMCR_BRANCH_ISSUED_MODE = 0x10 , PMCR_BRANCH_TAKEN_MODE = 0x11 , PMCR_SUBROUTINE_ISSUED_MODE = 0x12 , PMCR_INSTRUCTION_ISSUED_MODE = 0x13 , PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE = 0x14 , PMCR_FPU_INSTRUCTION_ISSUED_MODE = 0x15 , PMCR_INTERRUPT_COUNTER_MODE = 0x16 , PMCR_NMI_COUNTER_MODE = 0x17 , PMCR_TRAPA_INSTRUCTION_COUNTER_MODE = 0x18 , PMCR_UBC_A_MATCH_MODE = 0x19 , PMCR_UBC_B_MATCH_MODE = 0x1a , PMCR_INSTRUCTION_CACHE_FILL_MODE = 0x21 , PMCR_OPERAND_CACHE_FILL_MODE = 0x22 , PMCR_ELAPSED_TIME_MODE = 0x23 , PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE = 0x24 , PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE = 0x25 , PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE = 0x27 , PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE = 0x28 , PMCR_PIPELINE_FREEZE_BY_FPU_MODE = 0x29 }
	Performance Counter Event Modes. More...

Functions
bool	perf_cntr_config (perf_cntr_t counter, perf_cntr_event_t event_mode, perf_cntr_clock_t clock_type)
	Get a performance counter's settings.

void	perf_cntr_start (perf_cntr_t counter, perf_cntr_event_t event_mode, perf_cntr_clock_t clock_type)
	Start a performance counter.

void	perf_cntr_stop (perf_cntr_t counter)
	Stop a performance counter.

void	perf_cntr_resume (perf_cntr_t counter)
	Resume a performance counter.

void	perf_cntr_clear (perf_cntr_t counter)
	Clear a performance counter.

uint64_t	perf_cntr_count (perf_cntr_t counter)
	Obtain the count of a performance counter.

Detailed Description

SH4 CPU Performance Counter Driver

The performance counter API exposes the SH4's hardware profiling registers, which consist of two different sets of independently operable 48-bit counters.

Enumeration Type Documentation

◆ perf_cntr_clock_t

enum perf_cntr_clock_t

Count clock types for the SH4 performance counters.

Enumerator

PMCR_COUNT_CPU_CYCLES

CPU Cycles.

Count CPU cycles. At 5 ns increments (for 200Mhz CPU clock), a 48-bit cycle counter can run continuously for 16.33 days.

PMCR_COUNT_RATIO_CYCLES

Ratio Cycles.

Count CPU/bus ratio mode cycles (where T = C x B / 24 and T is time, C is count, and B is time of one bus cycle).

B has been found to be approximately 1/99753008, but actual time varies slightly. The target frequency is probably 99.75MHz.

◆ perf_cntr_event_t

enum perf_cntr_event_t

Performance Counter Event Modes.

This is the list of modes that are allowed to be passed into the perf_cntr_start() function, representing different events you want to count.

Enumerator
PMCR_INIT_NO_MODE	None; Just here to be complete.
PMCR_OPERAND_READ_ACCESS_MODE	Quantity; With cache.
PMCR_OPERAND_WRITE_ACCESS_MODE	Quantity; With cache.
PMCR_UTLB_MISS_MODE	Quantity.
PMCR_OPERAND_CACHE_READ_MISS_MODE	Quantity.
PMCR_OPERAND_CACHE_WRITE_MISS_MODE	Quantity.
PMCR_INSTRUCTION_FETCH_MODE	Quantity; With cache.
PMCR_INSTRUCTION_TLB_MISS_MODE	Quantity.
PMCR_INSTRUCTION_CACHE_MISS_MODE	Quantity.
PMCR_ALL_OPERAND_ACCESS_MODE	Quantity.
PMCR_ALL_INSTRUCTION_FETCH_MODE	Quantity.
PMCR_ON_CHIP_RAM_OPERAND_ACCESS_MODE	Quantity.
PMCR_ON_CHIP_IO_ACCESS_MODE	Quantity.
PMCR_OPERAND_ACCESS_MODE	Quantity; With cache, counts both reads and writes.
PMCR_OPERAND_CACHE_MISS_MODE	Quantity.
PMCR_BRANCH_ISSUED_MODE	Quantity; Not the same as branch taken!
PMCR_BRANCH_TAKEN_MODE	Quantity.
PMCR_SUBROUTINE_ISSUED_MODE	Quantity; Issued a BSR, BSRF, JSR, JSR/N.
PMCR_INSTRUCTION_ISSUED_MODE	Quantity.
PMCR_PARALLEL_INSTRUCTION_ISSUED_MODE	Quantity.
PMCR_FPU_INSTRUCTION_ISSUED_MODE	Quantity.
PMCR_INTERRUPT_COUNTER_MODE	Quantity.
PMCR_NMI_COUNTER_MODE	Quantity.
PMCR_TRAPA_INSTRUCTION_COUNTER_MODE	Quantity.
PMCR_UBC_A_MATCH_MODE	Quantity.
PMCR_UBC_B_MATCH_MODE	Quantity.
PMCR_INSTRUCTION_CACHE_FILL_MODE	Cycles.
PMCR_OPERAND_CACHE_FILL_MODE	Cycles.
PMCR_ELAPSED_TIME_MODE	Cycles For 200MHz CPU: 5ns per count in 1 cycle = 1 count mode. Around 417.715ps per count (increments by 12) in CPU/bus ratio mode
PMCR_PIPELINE_FREEZE_BY_ICACHE_MISS_MODE	Cycles.
PMCR_PIPELINE_FREEZE_BY_DCACHE_MISS_MODE	Cycles.
PMCR_PIPELINE_FREEZE_BY_BRANCH_MODE	Cycles.
PMCR_PIPELINE_FREEZE_BY_CPU_REGISTER_MODE	Cycles.
PMCR_PIPELINE_FREEZE_BY_FPU_MODE	Cycles.

◆ perf_cntr_t

enum perf_cntr_t

Identifiers for the two SH4 performance counters.

Enumerator

PRFC0

SH4 Performance Counter 0.

The first performance counter ID.

This counter is used by KOS by default to implement the Timer API. Reference it for details on how to reconfigure it if necessary.

PRFC1

SH4 Performance Counter 1.

The second performance counter ID.

This counter is not used anywhere internally by KOS.

Function Documentation

◆ perf_cntr_clear()

void perf_cntr_clear ( perf_cntr_t counter )

Clear a performance counter.

This function clears a performance counter. It resets its count to zero. This function stops the counter before clearing it because you cant clear a running counter.

Parameters

counter The counter to clear (i.e, PRFC0 or PRFC1).

◆ perf_cntr_config()

bool perf_cntr_config	(	perf_cntr_t	counter,
		perf_cntr_event_t *	event_mode,
		perf_cntr_clock_t *	clock_type )

Get a performance counter's settings.

This function returns a performance counter's settings.

Parameters

counter	The performance counter (i.e, PRFC0 or PRFC1).
event_mode	Pointer to fill in with the counter's event mode
clock_type	Pointer to fill in with the counter's clock type

Return values

true	The performance counter is running
false	the performance counter is stopped

◆ perf_cntr_count()

uint64_t perf_cntr_count ( perf_cntr_t counter )

Obtain the count of a performance counter.

This function simply returns the count of the counter.

Parameters

counter The counter to read (i.e, PRFC0 or PRFC1).

Returns: The counter's count.

◆ perf_cntr_resume()

void perf_cntr_resume ( perf_cntr_t counter )

Resume a performance counter.

This function resumes a stopped performance counter.

Parameters

counter The counter to resume (i.e. PRFC0 or PRFC1).

See also: perf_cntr_stop()

◆ perf_cntr_start()

void perf_cntr_start	(	perf_cntr_t	counter,
		perf_cntr_event_t	event_mode,
		perf_cntr_clock_t	clock_type )

Start a performance counter.

This function starts a performance counter.

Parameters

counter	The counter to start (i.e, PRFC0 or PRFC1).
event_mode	Use one of the 33 event modes (pef_cntr_event_t).
clock_type	PMCR_COUNT_CPU_CYCLES or PMCR_COUNT_RATIO_CYCLES.

See also: perf_cntr_stop(), perf_cntr_resume()

◆ perf_cntr_stop()

void perf_cntr_stop ( perf_cntr_t counter )

Stop a performance counter.

This function stops a performance counter that was started with perf_cntr_start(). Stopping a counter retains its count. To clear the count use perf_cntr_clear().

Parameters

counter The counter to stop (i.e, PRFC0 or PRFC1).

See also: perf_cntr_clear()

Topics

Files

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ perf_cntr_clock_t

◆ perf_cntr_event_t

◆ perf_cntr_t

Function Documentation

◆ perf_cntr_clear()

◆ perf_cntr_config()

◆ perf_cntr_count()

◆ perf_cntr_resume()

◆ perf_cntr_start()

◆ perf_cntr_stop()