DMA

Driver for the SH4's Direct Memory Access Controller More...

Files
file	dmac.h
	Macros to access the DMA controller registers.

Macros
#define	DMAC_BASE   0xffa00000
#define	DMAC_DMAOR   (*((vuint32 *)(DMAC_BASE + 0x40)))
	A register that dictates the overall operation of the DMAC.

DMA Source Address Registers (SAR0-SAR3)
These registers designate the source address for DMA transfers. Currently we only support 32-byte boundary addresses.
#define	DMAC_SAR0   (*((vuint32 *)(DMAC_BASE + 0x00)))
#define	DMAC_SAR1   (*((vuint32 *)(DMAC_BASE + 0x10)))
#define	DMAC_SAR2   (*((vuint32 *)(DMAC_BASE + 0x20)))
#define	DMAC_SAR3   (*((vuint32 *)(DMAC_BASE + 0x30)))

DMA Destination Address Registers (DAR0-DAR3)
These registers designate the destination address for DMA transfers. Currently we only support 32-byte boundary addresses.
#define	DMAC_DAR0   (*((vuint32 *)(DMAC_BASE + 0x04)))
#define	DMAC_DAR1   (*((vuint32 *)(DMAC_BASE + 0x14)))
#define	DMAC_DAR2   (*((vuint32 *)(DMAC_BASE + 0x24)))
#define	DMAC_DAR3   (*((vuint32 *)(DMAC_BASE + 0x34)))

DMA Transfer Count Registers (DMATCR0-DMATCR3)
These registers define the transfer count for each DMA channel. The count is defined as: num_bytes_to_transfer/32
#define	DMAC_DMATCR0   (*((vuint32 *)(DMAC_BASE + 0x08)))
#define	DMAC_DMATCR1   (*((vuint32 *)(DMAC_BASE + 0x18)))
#define	DMAC_DMATCR2   (*((vuint32 *)(DMAC_BASE + 0x28)))
#define	DMAC_DMATCR3   (*((vuint32 *)(DMAC_BASE + 0x38)))

DMA Channel Control Registers (CHCR0-CHCR3)
These registers configure the operating mode and transfer methodology for each channel. For DMAC_CHCR2, it should always be set to 0x12c1 (source address incremented, burst mode, interrupt disable, DMA enable). For DMAC_CHCR1 and DMAC_CHCR3, it would probably be set to 0x1241 (source address incremented, cycle steal mode, interrupt disable, DMA enable).
#define	DMAC_CHCR0   (*((vuint32 *)(DMAC_BASE + 0x0c)))
#define	DMAC_CHCR1   (*((vuint32 *)(DMAC_BASE + 0x1c)))
#define	DMAC_CHCR2   (*((vuint32 *)(DMAC_BASE + 0x2c)))
#define	DMAC_CHCR3   (*((vuint32 *)(DMAC_BASE + 0x3c)))

List of helpful masks to check operations
The DMAOR_STATUS_MASK captures the On-Demand Data Transfer Mode (Bit 15), Address Error Flag (Bit 2), NMI Flag (Bit 1), and DMAC Master Enable (Bit 0). The DMAOR_NORMAL_OPERATION is a state where DMAC Master Enable is active, and the On-Demand Data Transfer Mode is not set, with no address errors or NMI inputs.
#define	DMAOR_STATUS_MASK   0x8007
#define	DMAOR_NORMAL_OPERATION   0x8001

Detailed Description

Driver for the SH4's Direct Memory Access Controller

Macro Definition Documentation

DMAC_BASE

#define DMAC_BASE   0xffa00000

DMAC_CHCR0

#define DMAC_CHCR0   (*((vuint32 *)(DMAC_BASE + 0x0c)))

DMAC_CHCR1

#define DMAC_CHCR1   (*((vuint32 *)(DMAC_BASE + 0x1c)))

DMAC_CHCR2

#define DMAC_CHCR2   (*((vuint32 *)(DMAC_BASE + 0x2c)))

DMAC_CHCR3

#define DMAC_CHCR3   (*((vuint32 *)(DMAC_BASE + 0x3c)))

DMAC_DAR0

#define DMAC_DAR0   (*((vuint32 *)(DMAC_BASE + 0x04)))

DMAC_DAR1

#define DMAC_DAR1   (*((vuint32 *)(DMAC_BASE + 0x14)))

DMAC_DAR2

#define DMAC_DAR2   (*((vuint32 *)(DMAC_BASE + 0x24)))

DMAC_DAR3

#define DMAC_DAR3   (*((vuint32 *)(DMAC_BASE + 0x34)))

DMAC_DMAOR

#define DMAC_DMAOR   (*((vuint32 *)(DMAC_BASE + 0x40)))

A register that dictates the overall operation of the DMAC.

So far we only use it check the status of DMA operations.

DMAC_DMATCR0

#define DMAC_DMATCR0   (*((vuint32 *)(DMAC_BASE + 0x08)))

DMAC_DMATCR1

#define DMAC_DMATCR1   (*((vuint32 *)(DMAC_BASE + 0x18)))

DMAC_DMATCR2

#define DMAC_DMATCR2   (*((vuint32 *)(DMAC_BASE + 0x28)))

DMAC_DMATCR3

#define DMAC_DMATCR3   (*((vuint32 *)(DMAC_BASE + 0x38)))

DMAC_SAR0

#define DMAC_SAR0   (*((vuint32 *)(DMAC_BASE + 0x00)))

DMAC_SAR1

#define DMAC_SAR1   (*((vuint32 *)(DMAC_BASE + 0x10)))

DMAC_SAR2

#define DMAC_SAR2   (*((vuint32 *)(DMAC_BASE + 0x20)))

DMAC_SAR3

#define DMAC_SAR3   (*((vuint32 *)(DMAC_BASE + 0x30)))

DMAOR_NORMAL_OPERATION

#define DMAOR_NORMAL_OPERATION   0x8001

DMAOR_STATUS_MASK

#define DMAOR_STATUS_MASK   0x8007