Address Space

Basics of the SH4 Memory Map More...

Topics
	P4 memory region
	P4 SH-internal memory region (non-cacheable).

Files
file	memory.h
	Constants for areas of the system memory map.

Macros
#define	MEM_AREA_CACHE_MASK   0x1fffffff
	Mask a cache-agnostic address.
#define	MEM_AREA_U0_BASE   0x00000000
	U0 memory region base (cacheable).
#define	MEM_AREA_P0_BASE   0x00000000
	P0 memory region base (cacheable).
#define	MEM_AREA_P1_BASE   0x80000000
	P1 memory region base (cacheable).
#define	MEM_AREA_P2_BASE   0xa0000000
	P2 memory region base (non-cacheable).
#define	MEM_AREA_P3_BASE   0xc0000000
	P3 memory region base (cacheable).
#define	MEM_AREA_P4_BASE   0xe0000000
	P4 memory region base (non-cacheable)

Detailed Description

Basics of the SH4 Memory Map

The SH7750 Series physical address space is mapped onto a 29-bit external memory space, with the upper 3 bits of the address indicating which memory region will be used. The P0/U0 memory region spans a 2GB space with the bottom 512MB mirrored to the P1, P2, and P3 regions.

Macro Definition Documentation

MEM_AREA_CACHE_MASK

#define MEM_AREA_CACHE_MASK   0x1fffffff

Mask a cache-agnostic address.

This masks out the upper 3 bits of an address. This is used when it is necessary to access memory with a specified caching mode. This is needed for DMA and SQ usage as well as various MMU functions.

MEM_AREA_P0_BASE

#define MEM_AREA_P0_BASE   0x00000000

P0 memory region base (cacheable).

This is the base privileged mode memory address. It is cacheable as determined by the WT bit of the cache control register. By default KOS sets this to copy-back mode.

MEM_AREA_P1_BASE

#define MEM_AREA_P1_BASE   0x80000000

P1 memory region base (cacheable).

This is a modularly cachable memory region. It is cacheable as determined by the CB bit of the cache control register. That allows it to function in a different caching mode (copy-back v write-through) than the U0, P0, and P3 regions, whose cache mode are governed by the WT bit. By default KOS sets this to the same copy-back mode as the other cachable regions.

MEM_AREA_P2_BASE

#define MEM_AREA_P2_BASE   0xa0000000

P2 memory region base (non-cacheable).

This is the non-cachable memory region. It is most frequently for DMA transactions to ensure reads are not cached.

MEM_AREA_P3_BASE

#define MEM_AREA_P3_BASE   0xc0000000

P3 memory region base (cacheable).

This functions as the lower 512MB of P0.

MEM_AREA_P4_BASE

#define MEM_AREA_P4_BASE   0xe0000000

P4 memory region base (non-cacheable)

This offset maps to on-chip I/O channels.

MEM_AREA_U0_BASE

#define MEM_AREA_U0_BASE   0x00000000

U0 memory region base (cacheable).

This is the base user mode memory address. It is cacheable as determined by the WT bit of the cache control register. By default KOS sets this to copy-back mode.

KOS runs in privileged mode, so this is here merely for completeness.