P4 memory region

P4 SH-internal memory region (non-cacheable). More...

Topics
	Control Registers
	Addresses of control registers within the P4 area

Macros
#define	MEM_AREA_SQ_BASE   0xe0000000
	Store Queue (SQ) memory base.
#define	MEM_AREA_ICACHE_ADDRESS_ARRAY_BASE   0xf0000000
	Instruction cache address array base.
#define	MEM_AREA_ICACHE_DATA_ARRAY_BASE   0xf1000000
	Instruction cache data array base.
#define	MEM_AREA_ITLB_ADDRESS_ARRAY_BASE   0xf2000000
	Instruction TLB address array base.
#define	MEM_AREA_ITLB_DATA_ARRAY1_BASE   0xf3000000
	Instruction TLB data array 1 base.
#define	MEM_AREA_ITLB_DATA_ARRAY2_BASE   0xf3800000
	Instruction TLB data array 2 base.
#define	MEM_AREA_OCACHE_ADDRESS_ARRAY_BASE   0xf4000000
	Operand cache address array base.
#define	MEM_AREA_OCACHE_DATA_ARRAY_BASE   0xf5000000
	Instruction cache data array base.
#define	MEM_AREA_UTLB_ADDRESS_ARRAY_BASE   0xf6000000
	Unified TLB address array base.
#define	MEM_AREA_UTLB_DATA_ARRAY1_BASE   0xf7000000
	Unified TLB data array 1 base.
#define	MEM_AREA_UTLB_DATA_ARRAY2_BASE   0xf7800000
	Unified TLB data array 2 base.
#define	MEM_AREA_CTRL_REG_BASE   0xff000000
	Control Register base.

Detailed Description

P4 SH-internal memory region (non-cacheable).

Macro Definition Documentation

MEM_AREA_CTRL_REG_BASE

#define MEM_AREA_CTRL_REG_BASE   0xff000000

Control Register base.

This is the base address of all control registers

MEM_AREA_ICACHE_ADDRESS_ARRAY_BASE

#define MEM_AREA_ICACHE_ADDRESS_ARRAY_BASE   0xf0000000

Instruction cache address array base.

This offset is used for direct access to the instruction cache address array.

MEM_AREA_ICACHE_DATA_ARRAY_BASE

#define MEM_AREA_ICACHE_DATA_ARRAY_BASE   0xf1000000

Instruction cache data array base.

This offset is used for direct access to the instruction cache data array.

MEM_AREA_ITLB_ADDRESS_ARRAY_BASE

#define MEM_AREA_ITLB_ADDRESS_ARRAY_BASE   0xf2000000

Instruction TLB address array base.

This offset is used for direct access to the instruction TLB address array.

MEM_AREA_ITLB_DATA_ARRAY1_BASE

#define MEM_AREA_ITLB_DATA_ARRAY1_BASE   0xf3000000

Instruction TLB data array 1 base.

This offset is used for direct access to the instruction TLB data array 1.

MEM_AREA_ITLB_DATA_ARRAY2_BASE

#define MEM_AREA_ITLB_DATA_ARRAY2_BASE   0xf3800000

Instruction TLB data array 2 base.

This offset is used for direct access to the instruction TLB data array 2.

MEM_AREA_OCACHE_ADDRESS_ARRAY_BASE

#define MEM_AREA_OCACHE_ADDRESS_ARRAY_BASE   0xf4000000

Operand cache address array base.

This offset is used for direct access to the operand cache address array.

MEM_AREA_OCACHE_DATA_ARRAY_BASE

#define MEM_AREA_OCACHE_DATA_ARRAY_BASE   0xf5000000

Instruction cache data array base.

This offset is used for direct access to the operand cache data array.

MEM_AREA_SQ_BASE

#define MEM_AREA_SQ_BASE   0xe0000000

Store Queue (SQ) memory base.

This offset maps to the SQ memory region. RW to addresses from 0xe0000000-0xe3ffffff follow SQ rules.

See also

dc\sq.h

MEM_AREA_UTLB_ADDRESS_ARRAY_BASE

#define MEM_AREA_UTLB_ADDRESS_ARRAY_BASE   0xf6000000

Unified TLB address array base.

This offset is used for direct access to the unified TLB address array.

MEM_AREA_UTLB_DATA_ARRAY1_BASE

#define MEM_AREA_UTLB_DATA_ARRAY1_BASE   0xf7000000

Unified TLB data array 1 base.

This offset is used for direct access to the unified TLB data array 1.

MEM_AREA_UTLB_DATA_ARRAY2_BASE

#define MEM_AREA_UTLB_DATA_ARRAY2_BASE   0xf7800000

Unified TLB data array 2 base.

This offset is used for direct access to the unified TLB data array 2.