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Independent SDK for the Sega Dreamcast
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Macros | Typedefs | Functions
broadband_adapter.h File Reference
Networking » Drivers » Broadband Adapter

Broadband Adapter support. More...

#include <sys/cdefs.h>

Go to the source code of this file.

Macros

#define RT_IDR0   0x00
 MAC address 0 (RW 32bit, RO 16/8)
 
#define RT_IDR1   0x01
 MAC address 1 (Read-only)
 
#define RT_IDR2   0x02
 MAC address 2 (Read-only)
 
#define RT_IDR3   0x03
 MAC address 3 (Read-only)
 
#define RT_IDR4   0x04
 MAC address 4 (RW 32bit, RO 16/8)
 
#define RT_IDR5   0x05
 MAC address 5 (Read-only)
 
#define RT_RES06   0x06
 Reserved.
 
#define RT_RES07   0x07
 Reserved.
 
#define RT_MAR0   0x08
 Multicast filter 0 (RW 32bit, RO 16/8)
 
#define RT_MAR1   0x09
 Multicast filter 1 (Read-only)
 
#define RT_MAR2   0x0A
 Multicast filter 2 (Read-only)
 
#define RT_MAR3   0x0B
 Multicast filter 3 (Read-only)
 
#define RT_MAR4   0x0C
 Multicast filter 4 (RW 32bit, RO 16/8)
 
#define RT_MAR5   0x0D
 Multicast filter 5 (Read-only)
 
#define RT_MAR6   0x0E
 Multicast filter 6 (Read-only)
 
#define RT_MAR7   0x0F
 Multicast filter 7 (Read-only)
 
#define RT_TXSTATUS0   0x10
 Transmit status 0 (32bit only)
 
#define RT_TXSTATUS1   0x14
 Transmit status 1 (32bit only)
 
#define RT_TXSTATUS2   0x18
 Transmit status 2 (32bit only)
 
#define RT_TXSTATUS3   0x1C
 Transmit status 3 (32bit only)
 
#define RT_TXADDR0   0x20
 Tx descriptor 0 (32bit only)
 
#define RT_TXADDR1   0x24
 Tx descriptor 1 (32bit only)
 
#define RT_TXADDR2   0x28
 Tx descriptor 2 (32bit only)
 
#define RT_TXADDR3   0x2C
 Tx descriptor 3 (32bit only)
 
#define RT_RXBUF   0x30
 Receive buffer start address (32bit only)
 
#define RT_RXEARLYCNT   0x34
 Early Rx byte count (RO 16bit)
 
#define RT_RXEARLYSTATUS   0x36
 Early Rx status (RO)
 
#define RT_CHIPCMD   0x37
 Command register.
 
#define RT_RXBUFTAIL   0x38
 Current address of packet read (queue tail) (16bit only)
 
#define RT_RXBUFHEAD   0x3A
 Current buffer address (queue head) (RO 16bit)
 
#define RT_INTRMASK   0x3C
 Interrupt mask (16bit only)
 
#define RT_INTRSTATUS   0x3E
 Interrupt status (16bit only)
 
#define RT_TXCONFIG   0x40
 Tx config (32bit only)
 
#define RT_RXCONFIG   0x44
 Rx config (32bit only)
 
#define RT_TIMER   0x48
 A general purpose counter, any write clears (32bit only)
 
#define RT_RXMISSED   0x4C
 24 bits valid, write clears (32bit only)
 
#define RT_CFG9346   0x50
 93C46 command register
 
#define RT_CONFIG0   0x51
 Configuration reg 0.
 
#define RT_CONFIG1   0x52
 Configuration reg 1.
 
#define RT_RES53   0x53
 Reserved.
 
#define RT_TIMERINT   0x54
 Timer interrupt register (32bit only)
 
#define RT_MEDIASTATUS   0x58
 Media status register.
 
#define RT_CONFIG3   0x59
 Config register 3.
 
#define RT_CONFIG4   0x5A
 Config register 4.
 
#define RT_RES5B   0x5B
 Reserved.
 
#define RT_MULTIINTR   0x5C
 Multiple interrupt select (32bit only)
 
#define RT_RERID   0x5E
 PCI Revision ID (10h) (Read-only)
 
#define RT_RES5F   0x5F
 Reserved.
 
#define RT_MII_TSAD   0x60
 Transmit status of all descriptors (RO 16bit)
 
#define RT_MII_BMCR   0x62
 Basic Mode Control Register (16bit only)
 
#define RT_MII_BMSR   0x64
 Basic Mode Status Register (RO 16bit)
 
#define RT_AS_ADVERT   0x66
 Auto-negotiation advertisement reg (16bit only)
 
#define RT_AS_LPAR   0x68
 Auto-negotiation link partner reg (RO 16bit)
 
#define RT_AS_EXPANSION   0x6A
 Auto-negotiation expansion reg (RO 16bit)
 
#define RT_CONFIG5   0xD8
 Config register 5.
 
#define RT_MII_RESET   0x8000
 Reset the MII chip.
 
#define RT_MII_RES4000   0x4000
 Reserved.
 
#define RT_MII_SPD_SET   0x2000
 1 for 100 0 for 10.
 
#define RT_MII_AN_ENABLE   0x1000
 Enable auto-negotiation.
 
#define RT_MII_RES0800   0x0800
 Reserved.
 
#define RT_MII_RES0400   0x0400
 Reserved.
 
#define RT_MII_AN_START   0x0200
 Start auto-negotiation.
 
#define RT_MII_DUPLEX   0x0100
 1 for full 0 for half.
 
#define RT_MII_LINK   0x0004
 Link is present.
 
#define RT_MII_AN_CAPABLE   0x0008
 Can do auto negotiation.
 
#define RT_MII_AN_COMPLETE   0x0020
 Auto-negotiation complete.
 
#define RT_MII_10_HALF   0x0800
 Can do 10Mbit half duplex.
 
#define RT_MII_10_FULL   0x1000
 Can do 10Mbit full.
 
#define RT_MII_100_HALF   0x2000
 Can do 100Mbit half.
 
#define RT_MII_100_FULL   0x4000
 Can do 100Mbit full.
 
#define RT_CMD_RESET   0x10
 Reset the RTL8139C.
 
#define RT_CMD_RX_ENABLE   0x08
 Enable Rx.
 
#define RT_CMD_TX_ENABLE   0x04
 Enable Tx.
 
#define RT_CMD_RX_BUF_EMPTY   0x01
 Empty the Rx buffer.
 
#define RT_INT_PCIERR   0x8000
 PCI Bus error.
 
#define RT_INT_TIMEOUT   0x4000
 Set when TCTR reaches TimerInt value.
 
#define RT_INT_RXFIFO_OVERFLOW   0x0040
 Rx FIFO overflow.
 
#define RT_INT_RXFIFO_UNDERRUN   0x0020
 Packet underrun / link change.
 
#define RT_INT_LINK_CHANGE   0x0020
 Packet underrun / link change.
 
#define RT_INT_RXBUF_OVERFLOW   0x0010
 Rx BUFFER overflow.
 
#define RT_INT_TX_ERR   0x0008
 Tx error.
 
#define RT_INT_TX_OK   0x0004
 Tx OK.
 
#define RT_INT_RX_ERR   0x0002
 Rx error.
 
#define RT_INT_RX_OK   0x0001
 Rx OK.
 
#define RT_INT_RX_ACK   (RT_INT_RXFIFO_OVERFLOW | RT_INT_RXBUF_OVERFLOW | RT_INT_RX_OK)
 Composite RX bits we check for while doing an RX interrupt.
 
#define RT_TX_CARRIER_LOST   0x80000000
 Carrier sense lost.
 
#define RT_TX_ABORTED   0x40000000
 Transmission aborted.
 
#define RT_TX_OUT_OF_WINDOW   0x20000000
 Out of window collision.
 
#define RT_TX_STATUS_OK   0x00008000
 Status ok: a good packet was transmitted.
 
#define RT_TX_UNDERRUN   0x00004000
 Transmit FIFO underrun.
 
#define RT_TX_HOST_OWNS   0x00002000
 Set to 1 when DMA operation is completed.
 
#define RT_TX_SIZE_MASK   0x00001fff
 Descriptor size mask.
 
#define RT_RX_MULTICAST   0x8000
 Multicast packet.
 
#define RT_RX_PAM   0x4000
 Physical address matched.
 
#define RT_RX_BROADCAST   0x2000
 Broadcast address matched.
 
#define RT_RX_BAD_SYMBOL   0x0020
 Invalid symbol in 100TX packet.
 
#define RT_RX_RUNT   0x0010
 Packet size is <64 bytes.
 
#define RT_RX_TOO_LONG   0x0008
 Packet size is >4K bytes.
 
#define RT_RX_CRC_ERR   0x0004
 CRC error.
 
#define RT_RX_FRAME_ALIGN   0x0002
 Frame alignment error.
 
#define RT_RX_STATUS_OK   0x0001
 Status ok: a good packet was received.
 
#define RT_ERTH(n)   ((n) <<24)
 Early RX Threshold multiplier n/16 or 0 for none.
 
#define RT_RXC_MulERINT   0x00020000
 0 for Early Receive Interrupt only on familiar protocols 1 for any
 
#define RT_RXC_RER8   0x00010000
 1 sets the acceptance of runt error packets
 
#define RT_RXC_RXFTH(n)   ((n) <<13)
 2^(4+n) bytes from 0-6 (16b - 1Kb) or 7 for none
 
#define RT_RXC_RBLEN(n)   ((n) <<11)
 Set Rx ring buffer len to 16b + 2^(3+n) kb.
 
#define RT_RXC_MXDMA(n)   ((n) << 8)
 2^(4+n) bytes from 0-6 (16b - 1Kb) or 7 for unlimited
 
#define RT_RXC_WRAP   0x00000080
 0 to use wrapping mode or 1 to not (Ignored for 64Kb buffer length)
 
#define RT_RXC_9356SEL   0x00000040
 0 if EEPROM is 9346, 1 if 9356.
 
#define RT_RXC_AER   0x00000020
 Accept Error Packets.
 
#define RT_RXC_AR   0x00000010
 Accept Runt (8-64 byte) Packets.
 
#define RT_RXC_AB   0x00000008
 Accept Broadcast Packets.
 
#define RT_RXC_AM   0x00000004
 Accept Multicast Packets.
 
#define RT_RXC_APM   0x00000002
 Accept Physical Match Packets.
 
#define RT_RXC_AAP   0x00000001
 Accept Physical Address Packets.
 
#define RT_CONFIG1_LED1   0x80
 XXX DC bba has no LED, maybe repurposed.
 
#define RT_CONFIG1_LED0   0x40
 XXX DC bba has no LED, maybe repurposed.
 
#define RT_CONFIG1_DVRLOAD   0x20
 Sets the Driver as loaded.
 
#define RT_CONFIG1_LWACT   0x10
 LWAKE active mode.
 
#define RT_CONFIG1_MEMMAP   0x08
 Registers mapped to PCI mem space.
 
#define RT_CONFIG1_IOMAP   0x04
 Registers mapped to PCI I/O space.
 
#define RT_CONFIG1_VPD   0x02
 Enable Vital Product Data.
 
#define RT_CONFIG1_PMEn   0x01
 Power Management Enable.
 
#define RT_CONFIG4_RxFIFIOAC   0x80
 Auto-clear the Rx FIFO overflow.
 
#define RT_CONFIG4_AnaOff   0x40
 Turn off analog power.
 
#define RT_CONFIG4_LongWF   0x20
 Long Wake-up Frames.
 
#define RT_CONFIG4_LWPME   0x10
 LWake vs PMEB.
 
#define RT_CONFIG4_RES08   0x08
 Reserved.
 
#define RT_CONFIG4_LWPTN   0x04
 LWAKE Pattern.
 
#define RT_CONFIG4_RES02   0x02
 Reserved.
 
#define RT_CONFIG4_PBWake   0x01
 Disable pre-Boot Wakeup.
 
#define RT_CONFIG5_RES80   0x80
 Reserved.
 
#define RT_CONFIG5_BWF   0x40
 Enable Broadcast Wakeup Frame.
 
#define RT_CONFIG5_MWF   0x20
 Enable Multicast Wakeup Frame.
 
#define RT_CONFIG5_UWF   0x10
 Enable Unicast Wakeup Frame.
 
#define RT_CONFIG5_FIFOAddr   0x08
 Set FIFO address pointer.
 
#define RT_CONFIG5_LDPS   0x04
 Disable Link Down Power Saving mode.
 
#define RT_CONFIG5_LANW   0x02
 Enable LANWake signal.
 
#define RT_CONFIG5_PME_STS   0x01
 Allow PCI reset to set PME_Status bit.
 
#define BBA_TX_OK   0
 Transmit success.
 
#define BBA_TX_ERROR   -1
 Transmit error.
 
#define BBA_TX_AGAIN   -2
 Retry transmit again.
 
#define BBA_TX_NOWAIT   0
 Don't block waiting for the transfer.
 
#define BBA_TX_WAIT   1
 Wait, if needed on transfer.
 

Typedefs

typedef void(* eth_rx_callback_t) (uint8 *pkt, int len)
 Receive packet callback function type.
 

Functions

void bba_get_mac (uint8 *arr)
 Retrieve the MAC Address of the attached BBA.
 
void bba_set_rx_callback (eth_rx_callback_t cb)
 Set the ethernet packet receive callback.
 
int bba_tx (const uint8 *pkt, int len, int wait)
 Transmit a single packet.
 

Detailed Description

Broadband Adapter support.

This file contains declarations related to support for the HIT-0400 "Broadband Adapter". There's not really anything that users will generally have to deal with in here.

Author
Megan Potter